Sr. Principal Lead ASIC Verification Engineer

Date posted: 
June 01, 2017
Job Type: 
Scottsdale, AZ
Job ID: 

Title: Sr. Principal Asic Engineer

The Senior Advanced ASIC Verification Engineer position requires a Bachelor's Degree in Electrical, Computer or Systems Engineering, Computer Science or a related specialty or the equivalent experience, and a minimum of ten years of related experience. A Master’s Degree in related specialty and a minimum of eight years of related experience is preferred.

The successful candidate must have the following experience:
• Eight to ten years of experience leading/managing verification of FPGA/ASICSs
• Eight to ten years of experience using SystemVerilog for verification
• Five or more years of experience with Open Verification Methodology (OVM, Universal Verification Methodology (UVM) or Verification Methodology Manual (VMM). UVM is preferred.
• Development of verification matrix to ensure coverage of requirements
• Defining regression test suits
• Managing regression simulations
• Tracking and resolving design bugs
• Developing and applying SystemVerilog Assertions (SVA) within an assertion-based verification strategy
• Developing functional coverage (covergroups, cover points) to measure test effectiveness
• Developing random constraints to guide constrained random simulations
• Experienced with Direct Programming Interface (DPI)
• Experienced with developing testbench infrastructure (agents, drivers, monitors, interfaces, scoreboards, environments, etc.)
• Thoroughly familiar with communication between static (module-based) and dynamic (class-based) components within a test environment
• Experienced with test/stimulus development using transactions, sequences and sequencers